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Fabrication of Planar Back End of Line Compatible HfOx Complementary Resistive Switches Marina Labalette, Simon Jeannot, Serge Blonkowski, Yann Beilliard, Serge Ecoffey, Abdelkader Souifi, and Dominique Drouin, Member, IEEE

Abstract—This paper presents the fabrication, together with morphological and electrical characterizations of complementary resistive switches using the nanodamascene process. The as-fabricated devices are fully embedded in an insulating oxide, opening the way for further process steps such as three-dimensional monolithic integration. Complementary resistive switches electrical performance is consistent with resistive random access memories fabricated and characterized with the same procedurethat showed RO F F /RO N ratios of 100. Complementary operating voltages of Vth 1,3 = |0.8| V and Vth 2.4 = |1.1| V are obtained for 88 × 22 nm2 junction with a 6 nm thick HfOx junction. Index Terms—Complementary resistive switches (CRS), monolithic integration, non-volatile memory (NVM), resistive random access memory (ReRAM), switching oxide.

I. INTRODUCTION ESISTIVE random access memories (ReRAM) are considered as one very promising candidate for next generation storage devices. Whereas NAND flash technology is facing scaling limits, ReRAM indeed offers a relatively simple and low-cost structure with competitive electrical characteristics [1]. These advantages can be found in cost effective and high density passive ReRAM architectures such as 3D vertical ReRAM structures (VRRAM) [2], [3]. However in such devices the association of a rectifying element at each memory point is

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Manuscript received March 2, 2017; accepted April 11, 2017. Date of publication April 26, 2017; date of current version September 6, 2017. This work was supported in part by the Fonds de recherche du Qu´ebec - Nature et technologies and in part by the Natural Sciences and Engineering Research Council of Canada. The review of this paper was arranged by Associate Editor xxxx. (Corresponding author: Marina Labalette.) M. Labalette is with the Laboratoire Nanotechnologies Nanosyst`emes - CNRS UMI-3463 and the Institut Interdisciplinaire d’Innovation Technologique, Universit´e de Sherbrooke, Sherbrooke, QC J1K 0A5, Canada, with the STMicroelectronics, Crolles 38920, France, and also with the Institut des Nanotechnologies de Lyon (INL) - UMR CNRS 5270, Villeurbanne cedex 69621, France (e-mail: [email protected]). S. Jeannot and S. Blonkowski are with the STMicroelectronics, Crolles 38920, France (e-mail: [email protected]; [email protected]). Y. Beilliard, S. Ecoffey, and D. Drouin are with the Laboratoire Nanotechnologies Nanosyst`emes - CNRS UMI-3463 and the Institut Interdisciplinaire d’Innovation Technologique, Universit´e de Sherbrooke, Sherbrooke, QC J1K 0A5, Canada (e-mail: [email protected]; [email protected]; [email protected]). A. Souifi is with the Laboratoire Nanotechnologies Nanosyst`emes - CNRS UMI-3463, Universit´e de Sherbrooke, Sherbrooke, QC J1K 0A5, Canada, and also with the Institut des Nanotechnologies de Lyon (INL) - UMR CNRS 5270, Villeurbanne cedex 69621, France (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2017.2698205

needed to avoid sneak path currents flowing through neighboring cells, which decreases the array density and complicates the fabrication process [4]. Replacing the memory point by a complementary resistive switching (CRS) device, which consists of two anti-serially connected ReRAMs, is an alternative to prevent sneak currents while maintaining a strong downscaling potential [5]. In this context, the present paper proposes the fabrication and the characterization of TiN/HfOx /Ti/HfOx /TiN CRS devices achieved thanks to the nanodamascene process [6]. This innovative approach is free of advanced etching steps and offers a fundamentally different configuration from vertically stacked structures, as the conductive filament grows horizontally [7], [8]. Additionally, the nanodamascene process allows to fabricate both ReRAM and CRS devices on the same chip with the same number of fabrication steps. II. DEVICE FABRICATION The fabrication process has been designed to be compatible with back-end-of-line (BEOL) technology in order to widen CRS application options for 3D monolithic integration [9]. Both CRS and ReRAM devices were fabricated using the nanodamascene process resulting in fully embedded memories into a SiO2 matrix. Their fabrication processes are summarized in Fig. 1. The difference between the two process flows is the location of the first Ti electrode, which corresponds to the lateral electrode and the central electrode for ReRAM and CRS respectively. The first step (not shown in Fig. 1) consists in an UV lithography followed with an oxide dry etching step of 60 nm. Both steps define the electrical contacts pads and the 2 μm wide metal lines trenches connected to the device area where the ReRAM and CRS are fabricated. Then the 100 nm wide 50 nm deep devices trenches are fabricated through electron beam lithography (EBL) and oxide dry etching steps. Their dimensions are similar to what can be obtained with high-end industrial lithography systems. The resistive switching HfOx layer and the passive TiN/Ti electrodes are deposited thanks to three successive sputtering steps of 11 nm, 10 nm and 160 nm in thickness respectively. Deposition conditions of 60 W for the target power and 3.9 mTorr for the chamber pressure are used for the HfOx with a deposition rate of 1.1 nm/min. The TiN is deposited at 60 W and 2.4 mTorr with a deposition rate of 2.3 nm/min. The Ti is deposited in two steps: the first 50 nm are deposited at 40 W and 2.9 mTorr with a deposition rate of 0.36 nm/min in

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Fig. 1. Schematic representation of fabrication process of planar ReRAM (left) and CRS (right) memory cells. Horizontal Ti/HfOx /TiN junctions are embedded into a SiO2 matrix. Depths and thicknesses values are only given for ReRAM process flow as they are identical for CRS process flow. The Ti electrical contacts connect the 100 nm wide devices electrodes to the 2 μm wide metal lines patterned with UV lithography for electrical characterization purposes.

order to completely fill the narrow SiO2 trenches, whereas the 110 nm remaining are deposited at 100 W and 2.9 mTorr with a deposition rate of 1.4 nm/min. Planar devices are then obtained using a chemical mechanical planarization (CMP) step that reveals the surface of the vertical switching junctions and metallic electrodes. If needed, controlled over-polishing can be used to shrink the memory cell further in the out-of-plane direction for downscaling purposes for example. Finally, an EBL step is performed in order to allow the contact between lateral and/or central devices electrodes and the 2 μm wide metal lines linked to the electrical contact pads defined by the first UV lithography process step.

III. SWITCHING JUNCTION MORPHOLOGICAL CHARACTERIZATION Atomic force microscopy (AFM), energy-filtered transmission electron microscopy (EFTEM) and scanning TEM energy dispersive X-ray spectroscopy (STEM-EDX) characterizations have been performed in order to investigate the morphology of the switching junction and the integrity of both Ti/HfOx and HfOx /TiN interfaces after the full fabrication process. Fig. 2(b) shows a 2 × 0.8 μm² AFM scan of a 88 nm wide Ti/HfOx /TiN junction. Fig. 2(a) represents the corresponding ‘AB’ and ‘CD’ line scans performed parallel and perpendicular to the junction. ‘AB’ line scan indicates a less than 1 nm deep valley located at the Ti/HfOx /TiN interfaces, which represents less than 5% of the junction height. It indicates that the junction is well preserved thanks to a high quality deposition process offering strong

Fig. 2. (a) ‘AB’ and ‘CD’ lines scan perprendicular and parallel to the junction respectively. The maximum recorded peak is 2 nm high which confirms the good quality of both Ti/HfOx and HfOx /TiN interfaces. (b) AFM characterization of a fabricated device with a 88 × 22 nm2 switching junction.

enough interfaces to sustain the chemical mechanical action of the polishing. Additionally, no major dishing or over-polishing effect is observed as the ‘CD’ line scan only shows a 2 nm high peak between the SiO2 substrate and the TiN/Ti electrode. The roughness of a 1.5 × 0.5 μm2 AFM scan is less than 1 nm RMS which is compatible with further technological process steps such as 3D monolithic integration. Fig. 3 shows an EFTEM cross section of a Ti/HfOx /TiN switching junction after CMP and before electrical characterization. The SiO2 trench and effective switching junction heights are then precisely estimated to be respectively 37 nm and 22 nm. The integrity of the junction and its interfaces with the metal electrodes are also confirmed. Both HfOx and TiN sputtered

LABALETTE et al.: FABRICATION OF PLANAR BACK END OF LINE COMPATIBLE HFOx COMPLEMENTARY RESISTIVE SWITCHES

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Fig. 3. EFTEM cross section of a Ti/HfOx /TiN junction after CMP. Interfaces are clearly defined and HfOx layer is continuous and with a constant height on the left electrode. The Pt layer has been used only for characterization purposes. Fig. 5. I(V) linear plot of a de-embedding Ti structure. The structure is fabricated during the same process flow than the devices, the only difference with ReRAM or CRS devices being the absence of the HfOx switching junction. The I(V) plot confirms the ohmic contact between the Ti electrical contacts and the nanometric electrodes and sets the resistance of all the metal lines and pads to 10 kΩ.

thanks to the well optimized deposition and CMP steps of our nanodamascene process. No morphological defects have been revealed inside the Ti/HfOx /TiN junction and the junction dimensions have been precisely evaluated at 88 × 22 nm². IV. ELECTRICAL CHARACTERIZATION A. ReRAM Performance and Preliminary Retention Tests Fig. 4. STEM-EDX analysis of a Ti/HfOx /TiN junction after CMP. A 4 nm thick oxygen layer is visible on the Ti surface due to the native oxidation occurring after polishing. The Pt layer has been used only for characterization purposes.

films are continuous on the first patterned Ti electrode. The HfOx layer thickness has been targeted to be 11 nm at the bottom of the SiO2 trench and to result into a 6 nm thick layer on the Ti electrode side. This variation of the HfOx thickness alongside the layer is attributed to the sputtering deposition technique itself and the tool we used. The latter has been chosen because it is an efficient and cost effective technique allowing to deposit successively the three HfOx , TiN and Ti materials in the same deposition chamber, thus avoiding any ambient air contamination or oxidation. Fig. 4 features a STEM-EDX analysis of the same device, confirming the presence of a 4 nm thick titanium dioxide on the surface of the right electrode. This native oxide layer might impact the performance and the endurance of the memory due to the oxygen diffusion at the junction interfaces. However, the TiO2 being mostly localized on the surface of the Ti electrode, performance deterioration should be negligible. Nevertheless, an oxygen free passivation layer deposition right after the CMP will be systematically performed for next fabricated devices, to prevent or limit the formation of TiO2 and maximize the performance of the cell. The combination of AFM and TEM morphological analysis confirmed that the integrity of our interfaces are preserved

Prior to any electrical characterization of the ReRAM and CRS devices, a de-embedding structure made of a SiO2 trench filled with Ti during the HfOx /TiN/Ti sputtering deposition steps has been electrically characterized. The Ti structure has the exact same lateral dimensions than ReRAM or CRS electrodes and is located in the device area zone so that the CMP leads to the same residual trench height than for the devices. Fig. 5 shows a schematic view of this structure with the associated I(V) plot. From the linear plot can be confirmed that the total resistance of the routing lines is 10 kΩ and that the contact is ohmic between the Ti electrical contacts and the nanometric electrodes. This resistance will then be considered to calculate the real voltage applied at the device junction terminals VJ U N C T I O N from the total voltage VT O T applied during measurement. DC voltage measurements have been carried-out to analyze the resistive switching characteristics. Voltage sweeps were applied to the Ti electrode while the TiN electrode was grounded. This procedure was used to characterize the HfOx ReRAM operations of the SET, RESET and FORMING using a 1R configuration. No transistors have been exploited to limit the current in the junctions as in 1T/1R configurations. During the FORMING process, the Ti electrode, referred as the active electrode, enables the accumulation of oxygen ions to form an oxygen exchange layer (OEL). Yalon et al. [10] have recently demonstrated the conductive filament was growing from the OEL no matter where the positive polarity is applied during forming and if the counter electrode is inert.

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Fig. 6. Electroforming I(V) plot of a planar Ti/HfOx /TiN ReRAM device. Ic o m p l is set at 100 nA and V f is found to be 3.3 V. The conductive filament is growing from the Ti electrode towards the TiN electrode.

Fig. 7. Electrical characterization of a planar Ti/HfOx /TiN ReRAM showing the switching cycles with the abscissa V = V J U N C T I O N . The switching junction area is 88 × 22 nm² and features a 6 nm thick HfOx layer. Inset shows collapsing of the memory window after 50 switching cycles.

In our system the TiN electrode is inert and the conductive filament should grow from the Ti/HfOx interface towards the HfOx /TiN, as depicted in Fig. 6. Electroforming steps have been conducted on 20 devices with the same junction thicknesses and surfaces. A typical forming curve is shown in Fig. 6. Positive voltage is applied on the Ti electrode and the mean forming voltage is 3 V ± 0.3 V. Fig. 7 shows electrical characterization of a fabricated Ti/HfOx /TiN device. The voltage value VJ U N C T I O N in abscissa is the real voltage at the device terminals, evaluated thanks to the previously calculated resistance in Fig. 5. SET and RESET voltages, VS E T and VR E S E T respectively. SET and RESET operations occur around +0.5 V and −0.6 V respectively, typical RO F F /RO N ratio is around 100, RESET current IR E S E T around 140 μA and an external compliance Icom pl is set to 150 μA for SET operations. Those electrical values are comparable with what has been reported in the literature regarding advanced VRRAM structures [7]. More than 50 cycles have been performed on this device. For a larger number of cycles, a degradation of the RO F F value is observed which limits the device endurance. The inset of

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Fig. 8. Monitoring of preliminary retention test for a planar Ti/HfOx /TiN ReRAM structure during 30 min. The OFF state is V r e a d = +100 mV and the ON state is V r e a d = −100 mV.

Fig. 7 shows the endurance test performed on this memory cell. Switching cycles are conducted and the resistance value is read at VR E A D = +100 mV after each cycle. We see that the memory window is collapsing after 50 cycles due to the OFF state deterioration. As the configuration used is a 1R configuration, the compliance is set on the external parametric analyzer that leads to a RC delay over 1 μs. Due to the extremely fast transition during FORMING and SET operation ( VR E S E T and, as the ReRAM A and B are supposedly symmetrical, we could expect Vth2,4 ≈ × 2 VR E S E T . Positive and negative read margin are equal to 0.3 V. The read currents at ‘ON’ and ‘1’ or ‘0’ states are 0.13 mA and 0.015 mA respectively which gives a ratio of around 9. Nonlinearity, defined as the current ratio between Vr ead (ON) and 1/2 Vr ead , is 16 (0.13 mA vs 0.008 mA) which is in the range of what have been recently obtained on IrOx /GdOx /Al2 O3 /TiN CRS structures [19]. Fig. 11 depicts the failure mechanism observed on our planar TiN/HfOx /Ti/HfOx /TiN CRS device. Indeed we suppose the conductive filament to be deteriorated during the cycles, especially we guess an increase of its diameter or an increase of the gap between the two conductive filament broken parts. Considering the limited endurance of the ReRAM devices explained in the Section A. above, a similar phenomenon is reasonably expected. In Fig. 11 red discontinuous line and blue continuous line represent two consecutive switching cycles. The red discontinuous line in positive voltage shows a cycle when the

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Fig. 11. Deterioration of the switching cycles of a planar TiN/HfOx /Ti/HfOx /TiN CRS: during the cycle represented by discontinuous red line only the ReRAM B can perform a SET and a RESET. During the next cycle represented by continuous blue line the ReRAM A is able to perform a RESET thanks to the increased applied voltage V s t o p .

ReRAM B is able to experiment a SET but the ReRAM A is unable to perform a RESET. When the negative voltage is applied the ReRAM A, still in the ON state, doesn’t change its resistive state, whereas the ReRAM B experiments a RESET as expected, but at Vth4 = −1.2 V instead of − 1.1 V. When going back to positive voltage for the next switching cycle, the applied voltage Vstop is increased from +1.2 V to +1.8 V and the ReRAM A is this time able to perform a RESET with a Vth2 increased at +1.2 V (as represented by the blue continuous line). When applying negative voltage it appears that the ReRAM B is now unable to perform a RESET, probably because the applied voltage is not high enough to reform the conductive filament through the residual oxide gap. We link this phenomena to the lack of a rectifying element during the FORMING of each ReRAM separately and during the first SET of each individual ReRAM performed before testing the CRS entire cell. However this problem should not occur in the case of a more mature CRS technology in a production line with CRS memory devices arranged into a crossbar matrix for high density integration. Under this configuration the CRS central electrode would be left as a floating point. Transistors would be required for the selection of lines and columns in the logic part of the architecture but not at every single memory point as it is the case for the ReRAM crossbar structures [4]. CRS are indeed self-rectifying devices. The forming step would stay challenging without any access to the central electrode, but can be solved using forming free ReRAM devices as in [20] or playing on the forming current as in [21]. These electrical characterization results confirm that our nanodamascene process can be employed to successfully fabricate two anti-serially connected ReRAM. The fabricated CRS devices exhibit a behavior close to what is expected in comparison with the characterized ReRAM individual cells fabricated with the same technology, but also in comparison with previously reported CRS in the literature. Further work is on-going to improve the nonlinearity and the devices endurance, by using an oxygen free passivation layer after the CMP step for example,

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so that CRS could be integrated in high density memory arrays in the CMOS BEOL. In regards to high density memory applications, we would like to address some scaling considerations. Let’s consider a 3D matrix populated with our CRS devices. The minimum feature size corresponding to the BEOL of the technology node is called f. Taking into account the minimal dimensions of a CRS device and the space required for the interconnects in the three directions, the minimum pitch of an elementary cell realized with our nanodamascene process would be 3f × 3f. The ultimate achievable volumic density of this configuration would therefore be 9f²/n, where n is the number of stacked layer. As the shrinking of the CRS dimensions is only governed by the nanometric thicknesses of the switching oxide and the metallic electrodes deposited at the bottom and on the sides of the oxide trench, the subsequent minimal value of f could offer a density as low as the other promising technologies for future non-volatile memory integrations. V. CONCLUSION We have fabricated for the first time horizontal TiN/ HfOx /Ti/HfOx /TiN CRS cells fully buried into a SiO2 matrix using the nanodamascene process. Junctions’ morphological characterizations and ReRAM electrical measurements validated the integrity and the electrical performance of 6 nm thick switching junctions with an area of 88 × 22 nm². AFM surface scans and EFTEM cross sections confirmed low roughness, high interface strength and deposition uniformity of the switching junction. DC electrical tests have been conducted on 1R structures. Operating SET and RESET voltages of +0.5 V and −0.6 V, with a memory ratio of 100 and RESET currents of 140 μA have been obtained. The CRS structures electrical tests have shown operating voltages of Vth1,3 = |0.8| V and Vt2,4 = |1.1| V. In our case the devices switching endurance is encouraging but can be improved using a 1T/1R configuration to avoid the overshoot phenomena occurring during the FORMING operation for CRS and ReRAM devices and also during the SET operation for the ReRAM devices. However, if one consider CRS devices into a crossbar matrix for high density memory array integration, only one transistor is needed at the end of each selection lines, leaving the central CRS electrode floating. The electroforming step will be conducted on the entire CRS structure as in [20], [21] and the number of required transistors will then be reduced compared to a ReRAM architecture where a rectifying element is needed at each memory point (1T/1R), paving the way for 3D monolithic stacking. REFERENCES [1] D. S. Jeong et al., “Emerging memories: Resistive switching mechanisms and current status,” Rep. Prog. Phys., vol. 75, no. 7, Jul. 2012, Art. no. 076502. [2] I. G. Baek et al., “Realization of vertical resistive memory (VRRAM) using cost effective 3D process,” in Proc. 2011 Int. Electron Devices Meet., Dec. 2011, pp. 31.8.1–31.8.4. [3] H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. Kang, and H.-S. P. Wong, “HfOx based vertical resistive random access memory for cost-effective 3D crosspoint architecture without cell selector,” in Proc. 2012 Int. Electrond Devices Meet., Dec. 2012, vol. 2, pp. 20.7.1–20.7.4.

LABALETTE et al.: FABRICATION OF PLANAR BACK END OF LINE COMPATIBLE HFOx COMPLEMENTARY RESISTIVE SWITCHES

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